Core selection for applications running on multiprocessor systems based on core and application characteristics

ABSTRACT

Techniques for scheduling an application program running on a multiprocessor computer system are disclosed. Example methods include but are not limited to analyzing first, second, third, and fourth core components for any within-die process variation, determining an operating state of the first, second, third and fourth core components, selecting optimum core components for each component type with the aid of bloom filters, statically determining which core component types are used by the application program, and scheduling the application program to run on a core having an optimum core component for a core component type used by the application program.

REFERENCE To RELATED APPLICATIONS

This application is related to the following co-pending application, application Ser. No. ______ (Attorney Docket No. BVF01-015-US) entitled “Thread Throttling” filed ______.

BACKGROUND

As integrated-circuit technology continues to scale, process variation—the divergence of process parameters from their nominal specifications—is becoming an issue that cannot be ignored at the architecture and system levels. Indeed, variation has major implications, such as increased leakage power consumption in the chips and limited processor frequency improvements [1].

In the context of a Chip Multiprocessor (CMP) system, or components within a CMP system, within-die process variation in current and near-future technologies may cause individual cores in the chip to differ substantially in the amount of power they may consume and in the maximum frequency that they may support. This effect, which has been reported elsewhere [3] suggests that it is no longer accurate to think of large CMP systems as homogeneous systems.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure can be better understood from the following description and appended claims, taken in conjunction with the following drawings. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the disclosed subject matter. Understanding that these drawings depict only several embodiments in accordance with the disclosure and are, therefore, not to be considered limiting of its scope, the disclosure will be described with additional specificity and detail through use of the accompanying drawings.

FIG. 1 illustrates a computer system according to at least some embodiments of the present disclosure.

FIG. 2 illustrates an application program being executed by an operating system in accordance with at least some embodiments of the present disclosure, including a detailed view of each core of a multiprocessor in FIG. 2A and FIG. 2B.

FIG. 3 illustrates a schematic representation of an application program being divided into threads which issue requests sent to a memory controller in accordance with at least some embodiments of the present disclosure.

FIG. 4 illustrates a flowchart arranged in accordance with at least embodiments of the present disclosure.

DETAILED DESCRIPTION

The following description sets forth various examples along with specific details to provide a thorough understanding of claimed subject matter. It will be understood by those skilled in the art, however, that claimed subject matter may be practiced without some or more of the specific details disclosed herein. Further, in some circumstances, well-known methods, procedures, systems, components and/or circuits have not been described in detail in order to avoid unnecessarily obscuring claimed subject matter. In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The illustrative embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented here. It will be readily understood that the aspects of the present disclosure, as generally described herein, and illustrated in the Figures, can be arranged, substituted, combined, and designed in a wide variety of different configurations, all of which are explicitly contemplated and make part of this disclosure.

It is beneficial to intelligently schedule threads while considering the within-chip process variations. However, as the number of cores in a chip increases, determining which core would effectively execute a given thread becomes a complicated task.

As contemplated here, within-die process variations may cause individual cores in a CMP system to differ in both static power consumed and maximum frequency supported. Similarly, within-die process variation may cause components within individual cores in a CMP system to differ in both static power consumed and maximum frequency supported. In this environment, ignoring variation effects when scheduling applications or when scheduling threads from applications may be suboptimal.

Within-die process variation may cause components within individual cores, known as core components, to fail or to provide suboptimal performance. Core component may include, for example, a branch predictor, cache, a floating point unit, a specific type of bus such as a memory bus, and a forwarding circuit used in pipeline designs, a register file, or an instructions queue. If a core component fails or provides suboptimal performance, it may slow down the performance of a CMP system.

In these environments, ignoring the effects of within-die process variation may result in suboptimal performance of the entire CMP system. Some hardware components may be available which may be used in determining the effects of within-die process variation within a certain core. Indeed, sophisticated on-chip power monitors and controllers such as those in Intel's Foxton technology [4] may be used to measure and manage the power heterogeneity of the cores. Moreover, the ability to support multiple on-chip frequency domains and change the frequency of each core independently as in AMD's Quad-Core Opteron [2] may be used to exploit the frequency heterogeneity of the cores.

As a result, the present disclosure identifies that it may be advantageous to be aware of within-die process variations within a CMP system or within various core components within a CMP system and to schedule applications, or threads within an application, to save power or improve throughput. By scheduling applications in a variation-aware manner, taking into account the different power and frequency characteristics of each individual core, or by taking into account within-die process variation for core components within a specific core or cores, substantial savings in power or substantial increases in throughput may be attainable.

FIG. 1 illustrates a computer system arranged according to at least some embodiments of the present disclosure. FIG. 1 illustrates a computer 100 including a processor 110, memory 120 and one or more drives 130. The drives 130 and their associated computer storage media may provide storage of computer readable instructions, data structures, program modules and other data for the computer 100. Drives 130 may include an operating system 140, application programs 150, program modules 160, and database 180. Operating system 140 and/or application programs 150, for example, may include program instructions for causing the computer 100 to carry out the functions and/or operations specified in FIG. 4. Computer 100 may include user input devices 190 through which a user may enter commands and data. Input devices may include an electronic digitizer, a microphone, a keyboard and pointing device, commonly referred to as a mouse, trackball or touch pad. Other input devices may include a joystick, game pad, satellite dish, scanner, or the like.

These and other input devices may be coupled to processor 110 through a user input interface that may be coupled to a system bus or it may be connected by other interface or bus structures, such as a parallel port, game port or a universal serial bus (USB), or the like. Computer 100 may include peripheral output devices such as speakers, a printer, or a display 202, which may be connected through an output peripheral interface 194 or the like.

Computer 100 may operate in a networking environment using logical connections to one or more computers, such as a remote computer connected to network interface 196 The remote computer may be a personal computer, a server, a router, a network PC, a peer device or other common network node, and may include many or all of the elements described above relative to computer 100.

Networking environments may include offices, enterprise-wide area networks (WAN), local area networks (LAN), intranets and the Internet. In an example, computer 100 may be the source machine from which data is being migrated and the remote computer may comprise the destination machine, or vice versa. Source and destination machines may not be connected by a network 108 or any other means, but instead, data may be migrated via any media capable of being written by the source platform and read by the destination platform or platforms. In a LAN or WLAN networking environment, computer 100 may be connected to the LAN or WAN through a network interface 196 or an adapter. In a WAN networking environment, computer 100 may include a modem or other means for establishing communications over the WAN, such as the Internet or network 108. Other means of establishing a communications link between the computers may be used.

A computer peripheral may include any device coupled to the processor 110 and the memory 120 of the computer 100 through the system bus. A computer peripheral may include any device connected with the output peripheral interface, including the display 202, the printer, or speakers, drives 130, user input devices 190 such as the keyboard, the mouse, and the microphone, and the network interface 196. Components of the computer peripheral may include any device within a computer peripherals which may use power and may be any device, such as speakers, lighting elements such as light emitting diodes, or backlights used to provide lighting for displays, display elements, such as LCD, LED, OLED, CRT, or Plasma displays, or semiconductor chips such as a central processing unit (CPU), a graphic processing unit (GPU), memory. According to an embodiment, computer 100 may be connected in a networking environment such that the processor 110 and/or program modules 160 may perform power reduction and conservation with minimal detriment to the user experience.

In some examples, methods for scheduling an application program running in a computer system are described. The computer system may include a multiprocessor having first and second cores and an operating system running the application program. The first core may have first and second core components of first and second core component types, respectively. The second core may have third and fourth core components of first and second core component types, respectively. The method may include analyzing the first, second, third, and fourth core components for any within-die process variation, and determining the operating states of the first, second, third and fourth core components. The method may include selecting optimum core components for each component type and determining which core component types are used by the application program. The method may include scheduling the application program to run on the core having an optimum core component for a core component type used by the application program.

In some other examples, methods for scheduling a plurality of application programs running in a computer system are described. The computer system may include a multiprocessor having first and second cores and an operating system running the application programs. The first core may have first and second core components of first and second core component types, respectively. The second core may have third and fourth core components of first and second core component types, respectively. The method may include determining the operating states of the first, second, third and fourth core components, and selecting optimum core components for each component type. The method may include determining which core components types are used by each application program, and scheduling each application program to run on a core having an optimum core component for a core component type used by each application program.

In still other examples, method for scheduling an application program running in a computer system are described. The computer system may include first and second cores and an operating system running the application program. The first core may have first and second core components of first and second core component types, respectively. The second core may have third and fourth core components of first and second core component types, respectively. The method may include determining the operating states of the first, second, third and fourth core components, and determining which core component types are used by each application program. The method may include scheduling the application program to run on a core having an optimum core component for a core component type used by the application program.

FIG. 2 illustrates an application program being executed by an operating system in accordance with at least some embodiments of the present disclosure. As shown in FIG. 2, operating system 140 may execute an application program 150 from drives 130. Operating system 140 and/or application programs 150, for example, may include program instructions for causing the computer 100 to carry out the functions and/or operations specified in FIG. 4. Application program 150 may be any application, program, portion of a program, or thread, which may be executed by operating system 140 in multiprocessor 111. Application program 150 may load data 230 into memory 120 and accesses data 230 from memory 120 using a memory controller 210. Application program 150 may run multiple sub-applications called threads 220 to accomplish a task, such as loading and accessing data 230 into and from memory bank 122 of memory 120 using one or more requests 226. Threads 220 may be executed by application program 150. Application program 150 may divide the execution of a task into as many threads 220 as application programs deems necessary to accomplish that task. For example, if application program 150 is a word processing program with a document having multiple pages, and application program 150 is configured to accomplish the task of spell checking each page of the document, application program 150 may divide the task of spell checking the document into multiple threads 220 such that each thread 220 may spell check a portion of the document. Each thread 220 may be sent to multiprocessor 111 for execution. When executed within the multiprocessor 111, each thread 220 may produce requests 226 for data 230 within memory 120. The requests 226 may be sent to memory controller 210, which may organize the requests 226 so that multiprocessor 111 may operate efficiently.

In some embodiments, as shown in FIG. 2, multiprocessor 111 may include processors that may simultaneously execute more than one thread 220. Multiprocessor 111 may include multiple processors known as cores 412 and 512, or a single processor (only one of 412 or 512) which may run multiple threads 220 simultaneously, also known as a multithreaded processor. FIG. 2 illustrates an example multiprocessor 111 including two cores 412 and 512, but is not limited to any particular number of cores. The term “core” is used herein to refer to any device which may process a single thread and may refer to a processor or a portion within a processor that may process a single thread. A multithreaded processor may be referred to as a processor having multiple cores. A computer 100 having multiple processors may be referred to herein as a computer 100 having multiple cores.

FIG. 2A and FIG. 2B include a detailed view of multiprocessor 111, showing details of the cores 412 and 512, respectively. As shown, each core 412 or 512, may include core components 413 or 513, which may be elements within each core that may perform a set function or operation for the core. There may be varying types of core components 413 or 513, also known as core component types, which may include, for example, a branch predictor (415 or 515), cache (417 or 517), a floating point unit (419 or 519), a specific type of bus (421 or 521) such as a memory bus, or a forwarding circuit (423 or 523) used in pipeline designs, a register (425 or 525), or an instructions queue (427 or 527). If a core component 413 or 513 fails or provides suboptimal performance, it may slow down the performance of the core, and ultimately the multiprocessor 111. Furthermore, a core 412 may have, for example, a branch predictor 415, which may perform faster than a branch predictor 515 of a core 512. In such an example, an application program 150 which requires heavy use of a branch predictor, may perform better on the first core 412 than the second core 512.

FIG. 3 illustrates a schematic representation of an application program being divided into threads which issue requests sent to a memory controller in accordance with at least some embodiments of the present disclosure. As shown in FIG. 3, application 150 may be divided into multiple threads 220 _(a)-220 _(n), where n may represent the number of threads 220, and wherein each thread may perform a task for application 150 and may be executed on, for example, multiprocessor 111 of FIG. 2. The multiprocessor may be configured to receive and execute multiple threads 220 _(a)-220 _(n), individually or simultaneously, from application program 150. Each thread 220 executed on the multiprocessor may be executed independently from each other thread 220 and may issue multiple requests 226 _(a1)-226 _(no) for data 230 stored in memory 120, where the first index (a . . . n) represents the thread 220 associated with the request 226, and the second index (1 . . . o) represents the number of requests 226 associated with a particular thread 220.

Each core component 413 or 513 shown in FIG. 2A and FIG. 2B, when manufactured, may suffer from some degree of process variation, which may cause the core components to fail or to provide suboptimal performance. Process variation may refer to changes in semiconductor processing related parameters (e.g., parameters related to doping density, mobility, resistance, capacitance, inductance, gain, speed, bandwidth, threshold voltage, parasitic effects, leakage, etc.) beyond their nominal values and may result from manufacturing difficulties at small feature sizes, for example. For the purposes of modeling and analysis, variation may be broken down into die-to-die (D2D) variation (or core-to-core variation) and within-die (WID) variation (or within-core variation). WID process variation may be further divided into systematic and random effects. WID process variation may have a direct effect on core-to-core variation in power and frequency within a computer.

Example semiconductor processing parameters that may be affected by WID process variation, include, for example, threshold voltage (V_(th)) and effective gate length (L_(eff)). These example parameters may impact a transistor's switching speed and leakage power. Higher V_(th) and L_(eff) variation may correspond to higher variation in transistor speed (or bandwidth) across the chip. This may result in slower processors (or multiprocessors) or slower core components since the slower transistors within the processor or core components may determine the frequency of the processor or the performance of the core components within the processor. In a multiprocessor 111, different cores may support different frequencies and different core components within cores may have varying performance. Also, as V_(th) varies, transistor leakage may vary across the processor or multiprocessor. Low-V_(th) transistors may consume more power than high-V_(th) transistors save. As a result, with variation, processors and multiprocessors may consume substantially more leakage power. In a multiprocessor, different cores may have varying amounts of transistor leakage.

To model systematic variation, the processor or multiprocessor, or individual core components within a processor or multiprocessor, may be divided into a grid. Each grid point may be given one value of the systematic component of the parameter, which may be assumed to have a normal distribution with μ=0 and standard deviation σ_(sys). Systematic variation may be characterized by a spatial correlation, so that adjacent areas on a chip may have roughly the same systematic component values.

Random variation may occur at the level of individual transistors and it may be modeled analytically with a normal distribution with μ=0 and standard deviation σ_(ran). Since the random and systematic components may be normally distributed and independent, their effects may be additive.

In an environment with process variation, each processor core in a multiprocessor may consume a different amount of power and may support a different maximum frequency, resulting in variations in performance from one core to another. Additionally, each core component within a processor (or multiprocessor) core may consume a different amount of power and may support a different maximum frequency, resulting in variations in performance from one core to another. Moreover, certain core components may completely fail or perform in a suboptimal manner. As a result, cores having core components which fail or provide suboptimal performance may not perform certain application programs as efficiently as other application programs which rely more on those core components.

In various described embodiments, applications may be scheduled using an application scheduling algorithm, such as that described in FIG. 4, to maximize the performance of the multiprocessor or minimize the power usage of the multiprocessor, substantially as if the variation-affected multiprocessor was a heterogeneous system. In this environment, there may be two high-level design issues. The first may be whether the different cores of the multiprocessor may have to cycle at the same frequency (Uniform Frequency) or not (Non-Uniform Frequency). The second may be whether the frequency and voltage of the cores of the multiprocessor may be changed dynamically (DVFS) or not (no DVFS). For these configurations, the operating system or application programs may include a variation-aware application scheduling algorithm for application scheduling and power management to minimize power or maximize performance. The application scheduling algorithms may complement the other scheduling criteria that may be used by the operating system, such as priority, fairness, or starvation-avoidance. More information regarding application scheduling algorithms can be found in Radu Teodorescu and Joseph Torrellas, “Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors,” 2008 International Symposium on Computer Architecture (ISCA), pp. 363-374, 2008, all of which is incorporated by reference herein, except where inconsistent with the present application.

FIG. 4 illustrates a flowchart arranged in accordance with at least some embodiments of the present disclosure. Referring to FIG. 4, to improve the performance or minimize power usage characteristics of each individual core, application programs may be scheduled to run in a variation-aware manner on specific cores or core components by the operating system using an application scheduling algorithm 600. Application scheduling algorithm 600 may take into account process variation for core components within a specific core or cores, and may allow for substantial savings in power or substantial increases in throughput when operating application programs.

In use, the operating system and/or an application program may activate the application scheduling algorithm 600 at block 601, and application scheduling algorithm 600 may be arranged to analyze core components within each core of a multiprocessor for process variation, at block 602. When analyzing core components for process variation, the application scheduling algorithm 600 may be configured to determine whether the core component is functional or not, at block 604. If the core component is determined to be functional, the application scheduling algorithm 600 may be arranged to examine within-die process variation and/or die-to-die process variation and determine how well the core component functions when compared with other core components of the same type. In an example, if application scheduling algorithm 600 determines that a particular branch predictor is functional, it may compare the performance of that branch predictor to the performance of other branch predictors, or to that of a predetermined series measurements, such as average operating voltages and/or average operating frequencies for similar branch predictors. Upon comparing the performance of a core component to that of another core components of the same type, the application scheduling algorithm 600 may be arranged to note (e.g., record or store) the operating state of the core component as functional or non-functional and, if functional, the application scheduling algorithm 600 may be arranged to rate (e.g., rank or score) how well the core component functions, with regard to performance or power efficiency, for example, at block 606. The rating of how well the core component functions may be on a scale, such as a scale from 1.0 to 10.0, or any other reasonable scale.

Upon noting and rating each core component, application scheduling algorithm 600 may be arranged to determine which core components types may be used by each application program running on the operating system, or which core component types may be important for each application program, at block 608; this may take place during the compilation of the application. The compiler may generate information that describes which components are used by each application or thread. The algorithm 600 may schedule each application program to run on a core having at least one optimal core component of a core component type used by the application program, at block 610. An optimal core component may be a core component which may be functional and may have a functional operating state. In an example, an optimal core component may be a core component which may have an operating state having the highest ranking. In another example, an optimal core component may be a core component which may have an above average ranking. In an embodiment, application scheduling algorithm 600 may schedule the application program to run on a core having the most optimal core components of a core component types used by the application program.

The application scheduling algorithm 600 may determine which application program is scheduled to run on which core. For example, each core component may be labeled, such as a branch predictor may be labeled 1, a floating-point multiplier may be labeled 2, an integer multiplier may be labeled 3, etc. For each core, there may be a separate bloom filter, with each bloom filter storing the label(s) of the core components which are failing on the associated core. For example, if the branch predictor of a particular core is failing, then the associated bloom filter may include element 1, since 1 is the label of the branch predictor. When an application (or thread) is to be scheduled, the application scheduling algorithm 600 may check whether there is a match between the application requirement and capability of a particular core. For example, if the application requires a floating-point multiplier, it may check the bloom filters of individual cores and see whether they contain the element 2 (corresponding to the floating-point multiplier label). If the bloom filter table contains the element, the application may be scheduled on another core. If it does not, that core may be used for the application.

In various embodiments, the disclosed methods may be implemented as a computer program product for use with a computer system. Such implementations may include a series of computer instructions fixed either on a tangible medium, such as a computer readable medium (e.g., a diskette, CD-ROM, ROM, or fixed disk) or transmittable to a computer system, via a modem or other interface device, such as a communications adapter connected to a network over a medium. The medium may be either a tangible medium (e.g., optical or analog communications lines) or a medium implemented with wireless techniques (e.g., microwave, infrared or other transmission techniques). The series of computer instructions embodies all or part of the functionality previously described herein with respect to the system. Those skilled in the art should appreciate that such computer instructions can be written in a number of programming languages for use with many computer architectures or operating systems. Furthermore, such instructions may be stored in any memory device, such as semiconductor, magnetic, optical or other memory devices, and may be transmitted using any communications technology, such as optical, infrared, microwave, or other transmission technologies. It is expected that such a computer program product may be distributed as a removable medium with accompanying printed or electronic documentation (e.g., shrink wrapped software), preloaded with a computer system (e.g., on system ROM or fixed disk), or distributed from a server or electronic bulletin board over the network (e.g., the Internet or World Wide Web). Of course, some embodiments of the disclosed subject matter may be implemented as a combination of both software (e.g., a computer program product) and hardware. Still other embodiments of the disclosed subject matter are implemented as entirely hardware, or entirely software (e.g., a computer program product).

The herein described subject matter sometimes illustrates different components contained within, or connected with, different other components. It is to be understood that such depicted architectures are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected”, or “operably coupled”, to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being “operably couplable”, to each other to achieve the desired functionality. Specific examples of operably couplable include but are not limited to physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting components and/or logically interacting and/or logically interactable components.

With respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity.

It will be understood by those within the art that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “includes but is not limited to,” etc.). It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases “at least one” and “one or more” to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim recitation to inventions containing only one such recitation, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and/or “an” should typically be interpreted to mean “at least one” or “one or more”); the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should typically be interpreted to mean at least the recited number (e.g., the bare recitation of “two recitations,” without other modifiers, typically means at least two recitations, or two or more recitations). Furthermore, in those instances where a convention analogous to “at least one of A, B, and C, etc.” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., “a system having at least one of A, B, and C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). In those instances where a convention analogous to “at least one of A, B, or C, etc.” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., “a system having at least one of A, B, or C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). It will be further understood by those within the art that virtually any disjunctive word and/or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase “A or B” will be understood to include the possibilities of “A” or “B” or “A and B.”

While various embodiments of the disclosed subject matter have been described, it will be apparent to those of ordinary skill in the art that other embodiments and implementations are possible within the scope of the disclosure. Accordingly, the disclosed subject matter is not to be restricted except in light of the attached claims and their equivalents.

REFERENCES

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[2] J. Dorsey, S. Searles, M. Ciraula, S. Johnson, N. Bujanos, D. Wu, M. Braganza, S. Meyers, E. Fang, and R. Kumar, “An integrated quadcore Opteron processor,” in International Solid State Circuits Conference, February 2007.

[3] E. Humenay, D. Tarjan, and K. Skadron, “The impact of systematic process variations on symmetrical performance in chip multiprocessors,” in Design, Automation and Test in Europe, April 2007.

[4] R. McGowen, C. A. Poirier, C. Bostak, J. Ignowski, M. Millican, W. H. Parks, and S. Naffziger, “Power and temperature control on a 90-nm Itanium family processor,” Journal of Solid-State Circuits, January 2006. 

1. A method for scheduling an application program running in a computer system having multiple cores, comprising: analyzing a first plurality of core components of a first core component type for process variation; selecting a first optimum core component from the first plurality of core components, based on the analyzing of the first plurality of core components; and scheduling an application program to run on the first optimum core component.
 2. The method of claim 1, further comprising determining an application core component type used by the application program, wherein the application core component type is the first core component type.
 3. The method of claim 1, wherein the first core component type is selected from the group consisting of a branch predictor, a cache, a floating point unit, a bus, a forwarding circuit, a register file and an instructions queue.
 4. The method of claim 1, wherein the process variation is core-to-core process variation.
 5. The method of claim 1, wherein the analyzing comprises: determining an operating state of each of the first plurality of core components; and storing the operating state of each of the first plurality of core components in a bloom filter.
 6. The method of claim 1, wherein the analyzing comprises ranking each of the first plurality of core components.
 7. The method of claim 1, further comprising: analyzing a second plurality of core components of a second core component type for process variation; selecting a second optimum core component from the second plurality of core components, based on the analyzing of the second plurality of core components; and scheduling the application program to run on the second optimum core component.
 8. The method of claim 7, further comprising determining a first and second application core component types used by the application program, wherein the first and second application core component types are the first and second core component types.
 9. The method of claim 7, wherein the first and second core component types are independently selected from the group consisting of a branch predictor, a cache, a floating point unit, a bus, a forwarding circuit, a register file and an instructions queue.
 10. The method of claim 7, wherein the analyzing comprises: determining an operating state of each of the first and second plurality of core components; and storing the operating state of each of the first and second plurality of core components in a bloom filter.
 11. The method of claim 7, wherein the analyzing comprises ranking each of the first and second plurality of core components.
 12. The method of claim 7, wherein the first and second optimum core components are on different cores.
 13. A computer program product comprising software encoded in computer-readable media, for scheduling an application program running in a computer system having multiple cores, the software comprising instructions, operable when executed, to: analyze a first plurality of core components of a first core component type for process variation; select a first optimum core component from the first plurality of core components, based on analyzing of the first plurality of core components; and schedule an application program to run on the first optimum core component.
 14. The computer program product of claim 13, further comprising instructions, operable when executed, to determine an application core component type used by the application program, wherein the application core component type is the first core component type.
 15. The computer program product of claim 13, wherein the process variation is core-to-core process variation.
 16. The computer program product of claim 13, wherein the instructions to analyze comprise instructions, operable when executed, to: determine an operating state of each of the first plurality of core components; and store the operating state of each of the first plurality of core components in a bloom filter.
 17. The computer program product of claim 13, further comprising instructions, operable when executed, to: analyze a second plurality of core components of a second core component type for process variation; select a second optimum core component from the second plurality of core components, based on analyzing of the second plurality of core components; and schedule the application program to run on the second optimum core component.
 18. The computer program product of claim 17, wherein the first and second optimum core components are on different cores.
 19. A computer system, comprising: multiple cores, each of the multiple cores comprising core components of first and second core component types, computer-readable media, operably coupled to the multiple cores, wherein the computer-readable media includes computer executable instructions which when executed by the computer system configure the computer system to: analyze a first plurality of the core components of the first core component type for process variation; select a first optimum core component from the first plurality of core components, based on analyzing of the first plurality; and schedule the application program to run on the first optimum core component.
 20. The computer system of claim 19, the computer-readable media further including computer executable which when executed by the computer system further configure the computer system to: analyze a second plurality of core components of the second core component type for process variation; select a second optimum core component from the second plurality of core components, based on analyzing of the second plurality; and schedule the application program to run on the second optimum core component. 